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july 2011 doc id 17638 rev 4 1/20 20 STA335ML 2-channel microless high-e fficiency digital audio system sound terminal ? features wide supply voltage range (5.0 v to 26 v) powersso-36 exposed pad down package 2 channels of 24-bit ddx ? 100-db snr and dynamic range selectable 32 khz to 48 khz input sample rates automatic zero-detect mute automatic invalid input detect mute 2-channel i 2 s input data interface selectable clock input ratio (256 or 364 * fs) max power correction for lower full power 96-khz internal processing sample rate, 24-bit precision thermal overload and short-circuit protection embedded filterless configur ation capability applications lcds dvds cradles digital speakers wireless speaker cradles description the STA335ML is a single die embedding digital audio processing and high-efficiency power amplification, capable of operating without the aid of an external microcontroller. the STA335ML is part of the sound terminal ? family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. the STA335ML combines a unique 24-bit ddx ? digital class-d ternary modulator together with an extremely low r dson stereo power dmos stage. the latter is capable of a total output power of 2 x 20 w with outstanding performance in terms of efficiency (>90 %), thd, snr and emi. the microless feature allows its use in low-cost applications (cradle, digital speakers, audio terminals) where no microcontroller is needed. the serial audio data interface accepts the universally used i 2 s format. basic features, such as oversampling clock, gain, i 2 s format can be set using a minimal number of selection pins. the STA335ML is self-protected against thermal overload, overcurrent, short-circuit and overvoltage conditions. the fault condition is also signalled on an external pin (int_line) for specific requirements. powersso-36 with exposed pad down (epd) table 1. device summary order code package packaging STA335MLj powersso-36 epd tube STA335MLj13tr powersso-36 epd tape and reel www.st.com
STA335ML 2/20 doc id 17638 rev 4 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.5 electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.6 power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.7 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 fade-in/out feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 oversampling selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 gain selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7 power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 pll filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STA335ML block diagram doc id 17638 rev 4 3/20 1 block diagram figure 1. block diagram protection current/thermal logic regulators bias power control ddx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface
pin description STA335ML 4/20 doc id 17638 rev 4 2 pin description figure 2. pin connections (top view) table 2. pin description pin name type description 1 gnd_sub gnd substrate ground 2fmt in serial format: 0: i 2 s format 1: left justified 3 test_mode in this pin must be connected to ground 4 vss_reg analog internal reference at v cc - 3.3 v 5 vcc_reg analog internal v cc reference 6 out2b out output half-bridge 2b 7 gnd2 gnd power negative supply 8 vcc2 power power positive supply 9 out2a out output half-bridge 2a 10 out1b out output half-bridge 1b gnd_ s ub fmt te s t_mode v ss _reg vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd_reg config n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 3 6 3 5 3 4 33 3 2 3 1 3 0 2 9 2 8 27 26 25 24 2 3 22 21 20 1 9 vdd_dig gnd_dig gain on s el int_line re s et s di lrcki bicki xti gnd_pll filter_pll vdd_pll pwrdn gnd_dig vdd_dig n.c. n.c. ep, exposed pad (device ground)
STA335ML pin description doc id 17638 rev 4 5/20 11 vcc1 power power positive supply 12 gnd1 gnd power negative supply 13 out1a out output half-bridge 1a 14 gnd_reg analog internal ground reference 15 vdd_reg analog internal 3.3-v reference voltage 16 config in configuration mode, must be connected to ground 17 n.c. - no internal connection 18 n.c. - no internal connection 19 n.c. - no internal connection 20 n.c. - no internal connection 21 vdd_dig power positive supply digital 22 gnd_dig gnd digital ground 23 pwrdn in power down: 0: low-power mode 1: normal operation 24 vdd_pll power positive supply for pll 25 filter_pll in connection to pll filter 26 gnd_pll gnd negative supply for pll 27 xti in pll input clock, 256 * fs or 384 * fs 28 bicki in i 2 s serial clock 29 lrcki in i 2 s left/right clock 30 sdi in i 2 s serial data channel 31 reset in reset 32 int_line out fault interrupt 33 onsel in oversampling selector: 0: 256 * fs 1: 384 * fs 34 gain in gain selector: 0: 0 dbfs 1: 24 dbfs 35 gnd_dig gnd digital ground 36 vdd_dig power digital supply -ep - exposed pad for pcb heatsink, to be connected to ground plane table 2. pin description (continued) pin name type description
electrical specifications STA335ML 6/20 doc id 17638 rev 4 3 electrical specifications 3.1 absolute maximum ratings 3.2 thermal data 3.3 recommended operating conditions table 3. absolute maximum ratings symbol parameter min typ max unit v cc power supply voltage (pins vcc1, vcc2) - - 30 v v l logic input interface -0.3 - 4 v v dd digital supply (pin vdd_dig) - - 4 v t op operating junction temperature -20 - 150 c t stg storage temperature -40 - 150 c table 4. thermal data symbol parameter min typ max unit r th(j-case) thermal resistance junction to case (thermal pad) - 1.5 2 c/w t sd thermal shutdown junction temperature 140 - 150 c t hsd thermal shutdown hysteresis 18 20 22 c t w thermal warning temperature 120 130 140 c table 5. recommended operating conditions symbol parameter min typ max unit v cc power supply voltage (pins vcc1, vcc2) 5 - 26 v v l logic input interface 2.7 3.3 3.6 v v dd digital supply (pin vdd_dig) 2.7 3.3 3.6 v t amb ambient temperature -20 - 70 c
STA335ML electrical specifications doc id 17638 rev 4 7/20 3.4 electrical specificat ions - digital section table 6. electrical specifications for digital section 3.5 electrical specific ations - power section the specifications given here are with the operating conditions: v cc = 18 v, v dd = 3.3 v, f sw = 384 khz, t amb = 25 c, r l =8 unless otherwise specified. symbol parameter conditions min typ max unit i il input current without bias device v i = 0 v -10 - 10 a i ih v i = v dd = 3.6 v -10 - 10 a v il low-level input voltage - - - 0.2 * v dd v v ih high-level input voltage - 0.8 * v dd --v v ol low-level output voltage i ol = 2 ma - - 0.4 * v dd v v oh high-level output voltage i oh = 2 ma 0.8 * v dd --v i pu pull-up/down current - 25 66 125 a r pu equivalent pull-up/down resistance --50-k table 7. electrical specifications for power section symbol parameter conditions min typ max unit po output power btl thd = 1% - 16 - w thd = 10% - 20 - r dson on resistance of power p-channel/n-channel mosfet (total bridge) l d = 1 a - 180 250 m l dss power p-channel/n-channel leakage current v cc = 20 v --10 a gp power p-channel r dson matching l d = 1.5 a 95 - - % gn power n-channel r dson matching l d = 1.5 a 95 - - % i ldt low current deadtime (static) resistive load figure 4 - 8 15 ns i hdt high current deadtime (dynamic) load = 1.5 a ( figure 5 ) - 15 30 ns t r rise time resistive load figure 4 - 1018ns t f fall time resistive load figure 4 - 1018ns
electrical specifications STA335ML 8/20 doc id 17638 rev 4 i vcc supply current from v cc in power-down pwrdn = 0 - 0.1 1.0 ma supply current from v cc in operation pcm input signal = -60 dbfs. switching frequency = 384 khz no lc filters - 5260ma i vdd_dig supply current ddx processing (reference only) internal clock = 49.152 mhz - 5570ma i scp short-circuit protection hi-z output 4.0 4.2 - a uvl undervoltage protection threshold --3.54.3v t min output minimum pulse width no load 20 30 60 ns dr dynamic range - - 100 - db snr signal-to-noise ratio a-weighted - 100 - db thd+n total harmonic distortion + noise ddx stereo mode, po = 1 w, f = 1 khz -0.2-% psrr power supply rejection ratio ddx stereo, <5 khz vripple = 1 v rms audio input = dither only -80-db x ta l k crosstalk ddx stereo, <5 khz one chan. driven at 1 w other channel measured -80-db peak efficiency, ddx mode po = 2 x 20 w into 8 -90-% table 7. electrical specifications for power section (continued) symbol parameter conditions min typ max unit
STA335ML electrical specifications doc id 17638 rev 4 9/20 3.6 power-on sequence figure 3. power-on sequence 3.7 test circuits figure 4. resistive load figure 5. test circuit don?t c a re vcc xti re s et pwrdn tr don?t c a re vdd_dig tr don?t c a re don?t c a re tr don?t c a re tr don?t c a re tr = minim u m time b etween xti m as ter clock s t ab le a nd re s et remov a l: 1 m s note 1: clock s t ab le me a n s : f m a x - f min < 1 mhz note 2: no s pecific v cc a nd v dd t u rn-on s e qu ence i s re qu ired. low current dead time = max(dtr,dtf) outxy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% inxy outxy gnd +vcc m58 m57 r 8 + - v67 = vdc = vcc/2 d03au1458 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout iout q4 q1 q3 inb d03au1517_00 ina dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of iout in the direction shown in figure l68 22 l67 22 outa
functional description STA335ML 10/20 doc id 17638 rev 4 4 functional description 4.1 serial audio interface protocols the STA335ML serial audio input interfaces with standard digital audio components and accepts serial data formats. the STA335ML always acts as a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using 3 input pins: left/right clock lrcki (pin 29), serial clock bicki (pin 28), and serial data sdi (pin 30). the available formats are given in figure 6 and figure 7 . pin fmt (pin 2) selects the format such that fmt = logical 0 gives the i 2 s format and fmt = logical 1 gives the left-justified. figure 6. i 2 s figure 7. left-justified 1 n n -1 2 3 bicki sdi lrcki n n -1 n n -1 3 2 1 3 2 1 1 n n -1 n n -1 2 3 1 2 3 sdatai bicki lrcki
STA335ML functional description doc id 17638 rev 4 11/20 4.2 fault-detect recovery bypass the on-chip STA335ML power output block provides feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either overcurrent or thermal). when fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. this sequence is repeated for as long as the fault exists. 4.3 zero-detect mute enable if this function is enabled, the zero-detect ci rcuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. if so, the channel is muted. 4.4 fade-in/out feature the STA335ML has an internal fade-in / fade-out feature when powered on or off, or after a fault condition. 4.5 oversampling selector pin onsel (33) is used to configure the pll to accept 256 * fs or 384 * fs master clock. where fs is the i 2 s lrcki frequency: onsel = logical 0 gives 256 * fs onsel = logical 1 gives 384 * fs. 4.6 gain selector pin gain (34) is used to configure the STA335ML gain: gain = logical 0 gives 0 dbfs gain = logical 1 gives 24 dbfs. 4.7 power-down function pin pwrdn (23) is used to power down the STA335ML: pwrdn = logical 0 sets the power-down mode pwrdn = logical 1 gives normal operation. if the power stage is switched off, then the pll is also switched off. it is possible to use the pwrdn function as a mute function.
applications STA335ML 12/20 doc id 17638 rev 4 5 applications 5.1 applications schematic figure 10 on the next page shows the schematic of a typical application for the STA335ML. concerning the power supplies, take care when designing the pcb layout. in particular, the 3.3- resistors on the digital supplies (vdd_dig) must be placed as close as possible to the device. this helps to preven t parasitic oscillation in the digital part of the device due to the inductive tracks of the pcb. the same rule applies for all the decoupling capacitors in order to limit any spikes on the supply pins. 5.2 internal voltage reference an embedded voltage regulator produces the reference voltages for the dmos bridge driver. it requires two 100 nf capacitors to keep the regulator stable. the capacitors should be place close to the pins. figure 8. reference voltage block diagram 5.3 pll filter schematic it is recommended to use the circuit in figure 9 below for the pll loop filter to achieve the best performance from the device in general application. note that the ground of this filter scheme has to be connected to the ground of the pll without any resistive path. concerning the component values, please take into account that the greater is the filter bandwidth, the less is the lock time but the higher is the pll output jitter. figure 9. pll applications schematic vcc_reg vss_reg vdd_reg gnd_reg 100 nf 100 nf regulator input i 2 s driver p driver n level shifter interface gnd vcc filter_pll gnd_dig 680 pf 2k2 4.7 nf 100 pf gnd_pll ferrite bead
STA335ML applications doc id 17638 rev 4 13/20 figure 10. applications schematic
applications STA335ML 14/20 doc id 17638 rev 4 5.4 typical output configuration figure 11 , figure 12 and figure 13 show the typical output circuits used for the btl stereo mode. please refer to the application note for all the other recommended output configurations. figure 11. output configuration for stereo btl mode (8 ohm) out1a 100 nf 100 nf 100 nf 100 nf 6r2 6r2 330 pf 22r out1b 22 h 22 h left 470 nf out2a 100 nf 100 nf 100 nf 100 nf 6r2 6r2 330 pf 22r out2b 22 h 22 h right 470 nf
STA335ML applications doc id 17638 rev 4 15/20 figure 12. filterless output configuration the filterless application is more critical in terms of emi. it is quite important to follow the suggestions below: tracks from amplifier to speaker should be as short as possible. ferrite beads can be used (instead of coils) to improve emi performance. ? ferrite beads must have a low impedance in the audio band and high impedance at high frequencies. ? place ferrite beads as close as possible to the ic. ? ferrite filters must reduce emi above 1 mhz. ? fcc and ce authorities test radiated emission above 30 mhz. figure 13. filterless output configuration with snubber network the presence of snubber networks reduce the emi. the snubber networks should be placed as close as possible to the ic. out1a out1b out2a out2b right left out1a 330 pf 22 r out1b out2a 330 pf 22 r out2b right left
package thermal characteristics STA335ML 16/20 doc id 17638 rev 4 6 package thermal characteristics using a double layer pcb the thermal resistance junction to ambient with 2 copper ground areas of 3 x 3 cm 2 and with 16 via holes (see figure 14 ) is 24 c/w in natural air convection. the dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. the max estimated dissipated power for the STA335ML is: figure 14. double layer pcb with 2 copper ground areas and 16 via holes figure 15 shows the power derating curve for the powersso-36 package on a board with two copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 . figure 15. powersso-36 power derating curve 2 x 20 w into 8 , at 18 v pd max is approximately 4 w 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta333bw psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta333ml psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta333bw psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta333bw psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta333ml psso36 copper area 3x3 cm and via holes STA335ML powersso-36
STA335ML package mechanical data doc id 17638 rev 4 17/20 7 package mechanical data figure 16 on page 18 shows the package outline and the table below gives the dimensions. in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. table 8. powersso-36 epd dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g- - 0.10 - - 0.004 h 10.10 - 10.50 0.398 - 0.413 h- - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 4.90 - 7.10 0.193 - 0.280
package mechanical data STA335ML 18/20 doc id 17638 rev 4 figure 16. powersso-36 epd outline drawing h x 45
STA335ML revision history doc id 17638 rev 4 19/20 8 revision history table 9. document revision history date revision changes 09-may-2007 1 initial release. 20-feb-2008 2.0 application note added 29-sep-2008 2.1 package information updated 18-dec-2008 2.2 overcurrent limit removed 24-jun-2010 3 updated junction temperature range in table 3: absolute maximum ratings on page 6 updated table 7: electrical specifications for power section on page 7 removed max estimated dissipated power example on page 16 18-jul-2011 4 updated table 1: device summary removed lrclko, biclko, sdatao from figure 7 on page 10 updated figure 10: applications schematic on page 13 minor textual updates
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